Electronic circuits are rapidly becoming more multi-functioned, smaller, and lighter. In line with this trend, smaller, lighter, and thinner packages of semiconductor chips or the like and their mounting methods are also demanded.
To satisfy these demands, a flip-chip mounting technology is widely adopted, instead of wire-bonding technology, in technologies for mounting semiconductor chips on a wiring board. The flip-chip technology is to form projecting electrodes, using solder or Au wire, on the surface of a semiconductor chip and connect these electrodes to a wiring board. In this technology, in general, a semiconductor chip is mounted, via projecting electrodes, on one side of a wiring board with a wiring pattern, and resin called underfill is filled between the semiconductor chip and the wiring board, so as to integrate and fix the semiconductor chip onto the wiring board.
Since the semiconductor chip and the wiring board are integrated using resin, warpage occurs consistently or repeatedly due to heat treatment during production or external ambient temperature during use if a thermal expansion coefficient differs between the semiconductor chip and the wiring board.
To solve this warpage problem, a double-sided mounting method for chip mounting boards is disclosed. (For example, refer to Patent Literature 1.) The double-sided mounting method disclosed in Patent Literature 1 includes the first step of mounting the semiconductor chip on one face of the wiring board and curing underfill resin between the wiring board and the semiconductor chip, and the second step of mounting a semiconductor chip on the other face of the wiring board and curing underfill resin between the wiring board and the semiconductor chip. The use of underfill resin with different thermal expansion coefficients in the first step and the second step prevents warpage of the chip-mounted board.
However, the use of different types of underfill resin in Patent Literature 1 results in restrictions to flexibility in material designs. In addition, since steps of placing a semiconductor chip, injecting underfill resin, and curing underfill resin need to be implemented separately for the surface and the rear face of the wiring bard, the assembly time approximately doubles, decreasing the productivity. Accordingly, a technology for both improving productivity and suppressing warpage has been demanded. Still more, a temperature for canceling the warpage occurred in assembly processes may not be an optimal temperature for curing underfill resin. If the temperature is not optimal, curing of underfill resin may take longer time, curing of underfill resin may not be achieved, or contrarily, curing time may be too short. As a result, voids are produced in the underfill resin, and reliability reduces due to degradation in moisture resistance or bonding strength.
Still more, a mounting method for a structure with electronic component mounted therein and the mounting structure are disclosed. (For example, refer to Patent Literature 2.) In Patent Literature 2, the structure with electronic component mounted therein is mounted facing down on a wiring board with fine holes via liquid resin composite containing inorganic filler with the size larger than the holes. Since only resin in the liquid resin composite is filled in the holes, warpage of the structure with electronic component mounted therein is prevented, depending on an amount of resin filled in the holes, by adjusting thermal expansion coefficients of the resin composite between the electronic component and the wiring board.
Furthermore, a semiconductor device in which a semiconductor chip is mounted on both faces of a carrier tape with holes penetrating through is disclosed. (For example, refer to Patent Literature 3 and Patent Literature 4.) In Patent Literature 3 and Patent Literature 4, resin is filled between opposing semiconductor chips in a single step via a hole penetrating through, and the resin improves the sealing strength.
In the above Patent Literature 3, warpage of overall semiconductor device is effectively prevented when semiconductor chips are mounted on both faces of carrier tape. However, it is difficult to reduce a stress concentrated on a bonding section between an electrode of semiconductor chip and an electrode of tape carrier caused by difference in thermal expansion coefficients. Therefore, the stress concentrates on the bonding section by a change in external ambient temperature. This causes a crack, breakage, or peeling in the bonding section, reducing the reliability.
In Patent Literature 4, warpage of semiconductor device is prevented by optimizing the filling sequence of underfill resin injected to semiconductor chips with different sizes mounted on both faces. In addition, the underfill resin can be efficiently filled via the holes penetrating through. However, same as Patent Literature 3, it is also difficult to reduce a stress concentrated on a bonding section in Patent Literature 4.
Patent Literature 1: Japanese Patent Unexamined Publication No. 2004-23045
Patent Literature 2: Japanese Patent Unexamined Publication No. 3260249
Patent Literature 3: Japanese Patent Unexamined Publication No. H3-20051
Patent Literature 4: Japanese Patent Unexamined Publication No. 2007-134448